Advanced Hdl Synthesis and Soc Prototyping: Rtl Design Using Verilog
| AUTHOR | Taraate, Vaibbhav |
| PUBLISHER | Springer (01/18/2019) |
| PRODUCT TYPE | Hardcover (Hardcover) |
Description
Explains SOC architecture and micro-architecture design with case studies
Covers practical scenarios and issues, helpful to both students and professionals
Discusses systems design and testing scenarios using modern FPGAs
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Product Format
Product Details
ISBN-13:
9789811087752
ISBN-10:
981108775X
Binding:
Hardback or Cased Book (Sewn)
Content Language:
English
More Product Details
Page Count:
307
Carton Quantity:
22
Product Dimensions:
6.14 x 0.75 x 9.21 inches
Weight:
1.41 pound(s)
Feature Codes:
Illustrated
Country of Origin:
NL
Subject Information
BISAC Categories
Technology & Engineering | Electronics - Circuits - General
Technology & Engineering | Computer Architecture
Technology & Engineering | Logic Design
Dewey Decimal:
005.18
Descriptions, Reviews, Etc.
publisher marketing
Explains SOC architecture and micro-architecture design with case studies
Covers practical scenarios and issues, helpful to both students and professionals
Discusses systems design and testing scenarios using modern FPGAs
Show More
List Price $199.99
Your Price
$197.99